The present invention relates generally to the fabrication of semiconductor integrated circuit (IC) devices, and more particularly to magnetic random access memory (MRAM) devices.
Semiconductors are used for integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use an electron charge to store information.
A more recent development in memory devices involves spin electronics, which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. One such spin electronic device is a magnetic random-access memory (MRAM), which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is storable in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment""s alignment. The stored state is read from the element by detecting the component""s resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix structure having rows and columns.
An advantage of MRAMs compared to traditional semiconductor memory devices such as DRAMs is that MRAMs can be made smaller and provide a non-volatile memory.
For example, a personal computer (PC) utilizing MRAMs would not have a long xe2x80x9cboot-upxe2x80x9d time as with conventional PCs that utilize DRAMs. MRAMs permit the ability to have a memory with more memory bits on the chip than DRAMs or flash memories. Also, an MRAM does not need to be powered up and has the capability of xe2x80x9crememberingxe2x80x9d the stored data.
DRAMs differ from MRAMs in that, in a DRAM, a capacitor is typically used to store a charge indicative of the logic state, and an access field effect transistor (FET) is used to access the storage capacitor. The capacitors and FETs are manufactured within a substrate in the front-end-of-line (FEOL). In the back-end-of-line, (BEOL), metallization layers and via interconnect layers are formed on the substrate, to make electrical contact to the underlying storage capacitors, FETs and other active components on the DRAM.
MRAMs present some manufacturing challenges because in an MRAM, the storage cells comprising magnetic stacks must be manufactured in the BEOL. This is because the magnetic stacks must be electrically coupled to underlying and overlying conductive lines, which are manufactured in the BEOL.
Copper interconnects have been proposed for use in MRAM ICs due to their excellent conductive properties (e.g., low resistance), which enhance performance. However, copper oxidizes easily, which can be problematic, as described further herein.
During the formation of contact vias or trenches, copper conductive lines may be exposed in some areas.
For example, a wafer may be exposed to an oxygen plasma environment to strip a resist that is used to pattern the wafer. Exposed copper material oxidizes during a resist strip process and will form an oxide comprised of copper oxide on the surface thereof, for example. The formation of an oxide on copper conductive lines may be undesirable, because in certain semiconductor devices, copper conductive lines must make electrical contact to subsequently deposited layers and/or conductive lines. The presence of an oxide on a copper conductive line prevents electrical contact of conductive line with subsequently deposited conductive lines.
The problem of oxidizing first conductive lines during the formation of trenches for second conductive lines is particularly problematic in the manufacture of MRAMs and other magnetic memory devices because magnetic memory cells must be formed in contact with metallization layers comprising the first and second conductive lines in an array region of the wafer, while simultaneously forming conductive lines in a non-array region of the wafer.
Another problem with forming trenches and vias for conductive lines of a magnetic memory array is that etch processes to remove cap and liner layers of magnetic stacks or memory cells may erode the dielectric layer the trenches are being formed in, distorting the original pattern of the trenches. This is undesirable, as potential shorts can occur between underlying conductive lines and subsequently formed conductive lines.
What is needed in the art is a semiconductor device and method of fabrication thereof that reduces or prevents oxidation and/or shorts of copper conductive lines.
A preferred embodiment of the present invention achieves technical advantages as method of patterning conductive lines of a magnetic memory array that prevents oxidation of the conductive line material by using a hard metal mask rather than resist.
Disclosed is a method of manufacturing a semiconductor memory device, comprising forming first conductive lines over a substrate, and forming memory cells over the first conductive lines, where the first conductive lines are electrically coupled to the memory cells. A dielectric layer is deposited over the memory cells, and a hard metal mask is deposited over the dielectric layer. The dielectric layer is patterned with the hard metal mask to form trenches within the dielectric layer.
Also disclosed is a method of manufacturing a semiconductor memory device, comprising depositing a first dielectric layer over a substrate, forming first conductive lines within the first dielectric layer, and forming memory cells over the first conductive lines, where the first conductive lines are electrically coupled to the memory cells. A second dielectric layer is deposited between the memory cells, and a third dielectric layer is deposited over the second dielectric layer and the memory cells. A hard metal mask is deposited over the third dielectric layer, and a resist is deposited over the hard metal mask. The resist is patterned, and the hard metal mask is patterning with the resist. The resist is removed, and the third dielectric layer is patterned with the hard metal mask to form trenches for second conductive lines.
Advantages of a preferred embodiment of the invention include the ability to form second conductive lines of a memory IC without oxidizing underlying first conductive lines of the device. This is particularly advantageous in IC""s that use copper for the conductive line material, because copper easily oxidizes. A preferred embodiment of the invention is particularly beneficial in IC""s having different metallization layers that must make electrical contact, particularly in devices where a magnetic memory array is formed in one region, and typical electrical connections are made between metallization layers in non-memory array regions.
Another advantage includes achieving a more accurate pattern of second conductive line trenches, preventing shorts.
The method and structure described herein may be used and applied to a variety of semiconductor devices, including memory integrated circuits, such as MRAM""s, DRAM""s and FRAM""s.